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CERNET High Speed Data Link
CERN-OBJ-IT-049 · Item · 1975
Parte de Heritage Collection Test

This card, based on a "4 slot DEC module", arbitrated the access priority of 15 datalinks of a CERNET node. Each datalinks could transfer data full duplex at 2.5 Mbit/sec over 1 Km of twisted pair (POD) cable. This was the frontier technology in 1980. The modest amount of integrated circuits was compensated by printing on the board photographs of the hardware designers, whose Belgian, Dutch and French nationality was underlined by the the short poem.

DLT 2000 (CompactTape III)
CERN-OBJ-IT-057 · Item · 1994
Parte de Heritage Collection Test

It has been introduced at CERN in 1994 and used until recently in the DEC TL820 robot. It has a capacity of 10 GB and 1.25 MB/s.

Bus and Tag Terminators for IBM system/360
CERN-OBJ-IT-074 · Item
Parte de Heritage Collection Test

Control units were connected to the channels with "Bus and Tag" cable pairs. The bus cables carried the address and data information and the tag cables identified what data was on the bus. There were three general types of bus-and-tag cables produced by IBM.

Dual-core Itanium Processor
CERN-OBJ-IT-081 · Item · 2006
Parte de Heritage Collection Test

Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

Wafer of Intel Pentium 4 Prescott Chips
CERN-OBJ-IT-084 · Item
Parte de Heritage Collection Test

Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.